- Generated on Wed Feb 19 2014 14:47:00 for POK(kernelpart) by
1.7.6.1
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POK(kernelpart)
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#include <types.h>Go to the source code of this file.
Defines | |
| #define | LEON_CTX_NBR 256 |
PTD/PTE ET field | |
(cf SPARC V8 Manual, page 247) | |
| #define | MM_ET_INVALID 0x0 |
| #define | MM_ET_PTD 0x1 |
| #define | MM_ET_PTE 0x2 |
PTE ACC field | |
Acces permisions. (cf SPARC V8 Manual, page 248) | |
| #define | MM_ACC_R (0x0 << 2) |
| #define | MM_ACC_RW (0x1 << 2) |
| #define | MM_ACC_RE (0x2 << 2) |
| #define | MM_ACC_RWE (0x3 << 2) |
| #define | MM_ACC_E (0x4 << 2) |
| #define | MM_ACC_R_S_RW (0x5 << 2) |
| #define | MM_ACC_S_RE (0x6 << 2) |
| #define | MM_ACC_S_RWE (0x7 << 2) |
PTE misc fields | |
(cf SPARC V8 Manual, page 248) | |
| #define | MM_CACHEABLE (1 << 7) |
| #define | MM_MODIFIED (1 << 6) |
| #define | MM_REFERENCED (1 << 5) |
MMU levels utils | |
| #define | MM_LVL1_ENTRIES_NBR 256 |
| #define | MM_LVL1_PAGE_SIZE (64 * 64 * 4 * 1024) |
| #define | mm_index1(addr) (((addr) >> 24) & 0xFF) |
| #define | MM_LVL2_ENTRIES_NBR 64 |
| #define | MM_LVL2_PAGE_SIZE (64 * 4 * 1024) |
| #define | mm_index2(addr) (((addr) >> 18) & 0x3F) |
| #define | MM_LVL3_ENTRIES_NBR 64 |
| #define | MM_LVL3_PAGE_SIZE (4 * 1024) |
| #define | mm_index3(addr) (((addr) >> 12) & 0x3F) |
MMU ASI and registers | |
| #define | ASI_M_MMUREGS 0x19 /* not sparc v8 compliant */ |
| #define | MMU_CTRL_REG 0x00000000 |
| #define | MMU_CTXTBL_PTR 0x00000100 |
| #define | MMU_CTX_REG 0x00000200 |
| #define | MMU_FAULT_STATUS 0x00000300 |
| #define | MMU_FAULT_ADDR 0x00000400 |
Typedefs | |
| typedef uint32_t | pte |
| typedef uint32_t | ptd |
Functions | |
| void | pok_arch_space_init (void) |
Definition in file space.h.
| #define ASI_M_MMUREGS 0x19 /* not sparc v8 compliant */ |
| #define LEON_CTX_NBR 256 |
| #define MM_ACC_R_S_RW (0x5 << 2) |
| #define MM_ACC_RWE (0x3 << 2) |
| #define MM_ACC_S_RE (0x6 << 2) |
| #define MM_ACC_S_RWE (0x7 << 2) |
| #define MM_CACHEABLE (1 << 7) |
| #define MM_ET_INVALID 0x0 |
| #define mm_index1 | ( | addr | ) | (((addr) >> 24) & 0xFF) |
| #define mm_index2 | ( | addr | ) | (((addr) >> 18) & 0x3F) |
| #define mm_index3 | ( | addr | ) | (((addr) >> 12) & 0x3F) |
| #define MM_LVL1_ENTRIES_NBR 256 |
| #define MM_LVL1_PAGE_SIZE (64 * 64 * 4 * 1024) |
| #define MM_LVL2_ENTRIES_NBR 64 |
| #define MM_LVL2_PAGE_SIZE (64 * 4 * 1024) |
| #define MM_LVL3_ENTRIES_NBR 64 |
| #define MM_LVL3_PAGE_SIZE (4 * 1024) |
| #define MM_MODIFIED (1 << 6) |
| #define MM_REFERENCED (1 << 5) |
| #define MMU_CTRL_REG 0x00000000 |
| #define MMU_CTX_REG 0x00000200 |
| #define MMU_CTXTBL_PTR 0x00000100 |
| #define MMU_FAULT_ADDR 0x00000400 |
| #define MMU_FAULT_STATUS 0x00000300 |
| void pok_arch_space_init | ( | void | ) |
1.7.6.1